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IDT5V41066
4 OUTPUT PCIE GEN1/2 SYNTHESIZER
IDT 4 OUTPUT PCIE GEN1/2 SYNTHESIZER
10
IDT5V41066
REV D 112211
AC Electrical Characteristics - CLKOUT (A:D)
Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85
° C
1 Test setup is R
S=33Ω, RP=50Ω with CL=2 pF, Rr = 475Ω (1%).
2 Measurement taken from a single-ended waveform.
3 Measurement taken from a differential waveform.
4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.
5 CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its
PD= low.
Electrical Characteristics - Differential Phase Jitter
Note 1. Guaranteed by design and characterization, not 100% tested in production.
Note 2. See http://www.pcisig.com for complete specs.
Note 3: Applies to 100MHz, spread off and 0.5% down spread only.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
25
MHz
Output Frequency
HCSL termination
25
200
MHz
LVDS termination
25
100
MHz
Output High Voltage1,2
VOH
HCSL
850
mV
Output Low Voltage1,2
VOL
HCSL
-150
mV
Crossing Point Voltage1,2
Absolute
250
550
mV
Crossing Point Voltage1,2,4
Variation over all edges
140
mV
Jitter, Cycle-to-Cycle1,3
100
ps
Frequency Synthesis Error
All outputs
0
ppm
Modulation Frequency
Spread spectrum
30
32.9
33
kHz
Rise Time1,2
tOR
From 0.175 V to 0.525 V
175
700
ps
Fall Time1,2
tOF
From 0.525 V to 0.175 V
175
700
ps
Rise/Fall Time Variation1,2
125
ps
Output to Output Skew
50
ps
Duty Cycle1,3
45
55
%
Output Enable Time5
All outputs
50
100
ns
Output Disable Time5
All outputs
50
100
ns
Stabilization Time
tSTABLE
From power-up VDD=3.3 V
1.8
ms
Spread Spectrum Transition
Time
tSPREAD
Stabilization time after spread
spectrum changes
730
ms
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
Jitter, Phase
tjphasePLL
PCIe Gen1
30
86
ps (p-p)
1,2,3
tjphaseLO
PCIe Gen2, 10 kHz < f < 1.5 MHz
0.76
3
ps (RMS)
1,2,3
tjphaseHIGH PCIe Gen2, 1.5 MHz < f < Nyquist (50 MHz)
2.0
3.1
ps (RMS)
1,2,3
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